Semiconductor processing improvements and sophisticated design tools have allowed for more and more functions to be integrated together on a single integrated circuit (IC) chip. Such improvements allowed for cache memories to be integrated onto the same chip as a central processing unit (CPU) core. More recently, multiple CPU cores are being integrated onto the same chip along with one or more memories. As this trend continues, multiple CPU cores and multiple memory blocks will be integrated together.
FIG. 1 shows a multi-processor system chip. Processor cores 10, 10′, 10″ are integrated together onto IC chip 20. Each processor core may execute a separate stream of instructions and each accesses its own local cache memory, caches 12, 12′, 12″. When data is not found in the local cache memory (a cache miss), memory controllers 14, 14′, 14″ fetch the desired data from an external memory, such as using an external bus to a large external main memory.
Snoop tags 16 contain directory information about the entries currently being stored in caches 12, 12′, 12″. Cache coherency is achieved through the use of snoop tags 16, perhaps in conjunction with external directories and other controllers.
Self-test logic and test controllers may also be integrated onto a very-large-scale-integration (VLSI) chip. Test controller 18 may be included on IC chip 20. Test controller 18 may be activated by a combination or sequence of signals on external pins that activates a test mode.
FIG. 2 shows prior-art test scan chains in a large chip. Test scan chains are often inserted into chips to aid automated testing. Special chip-design software can replace ordinary D-type flip-flops with testable or scan flip-flops 30 that have two D inputs and 2 clocks. The extra clock inputs to scan flip-flops 30 are driven by test clock TCK, which can be applied to an external pin of the chip and may be buffered or gated (not shown). The normal clocks are stopped during test mode and TCK is pulsed to scan in and out data along the scan chains. The extra D inputs to scan flip-flops 30 are connected to Q outputs of other scan flip-flops 30 to form a scan chain along scan flip-flops 30.
The first scan flip-flops 30 in the scan chain has a second D input that receives a test-input TI from an external pin, while the last Q output from the last scan flip-flop of the chain of scan flip-flops 30 drives a test output TO that can be read by an external tester and compared to expected data by the external tester.
When a large chip has multiple CPU blocks 22, 22′, 22″, the Q output of the last scan flip-flop 30 in one CPU block 22 can drive the D test input of the first scan flip-flop 30 in second CPU block 22′. Likewise, the Q output of the last scan flip-flop 30 in second CPU block 22′ can drive the D test input of the first scan flip-flop 30 in third CPU block 22″. Thus test scan chains of scan flip-flops 30 in CPU blocks 22, 22′, 22″ may be chained together into one long scan chain.
While useful, the length of the long scan chain of scan flip-flops 30 through many CPU blocks 22, 22′, 22″ can be excessively long, requiring many pulses of test clock TCK to scan data in and out. Testing may be inefficient, increasing test times and test costs. Isolating test failures to particular CPU blocks may be quite difficult since the scan chains from different blocks are strung together into one long scan chain. The tester log file may have to be examined to determine which of CPU blocks 22, 22′, 22″ caused the test failure.
Further, when one of CPU blocks 22, 22′, 22″ has a defect that causes the CPU block to fail, the scan chain may be faulty too. A defect within the scan chain, although occurring in only one of CPU blocks 22, 22′, 22″, may prevent testing of other CPU blocks 22, 22′, 22″. Thus the entire chip fails when a single defect in one of CPU blocks 22, 22′, 22″ occurs that blocks the scan chain to other CPU blocks 22, 22′, 22″.
CPU blocks 22, 22′, 22″ could have separate scan chains, but then multiple test outputs TO would be generated from the multiple CPU blocks 22, 22′, 22″. Many chip pins might be needed for the multiple TO test outputs, and the external tester would have to compare expected data to the actual data from the many TO pins.
What is desired is test logic for a more complex multi-processor chip. An on-chip test system that can test multiple CPU cores independently of one another is desirable. Test scan chains and test controllers that can test multiple CPU cores in parallel is desirable. Test scan chains that can isolate faults in redundant processor cores are also desirable.